1. Field of the Invention
This invention relates to the system architecture of a computer graphics display system. More particularly this invention relates to clock circuits for sequencing pixel data in a memory display interface.
2. Art Background
In a typical computer graphics system, a frame buffer comprised of video random access memory (VRAM) stores pixel data for a display device. Usually the VRAM frame buffer is coupled to a RAMDAC device, which implements look-up table and digital to analog converter functions. The look-up tables of the RAMDAC convert pixel data received from the VRAM frame buffer into color pixel data. The digital to analog converter of the RAMDAC converts the color pixel data into analog video signals for the display device. However, a RAMDAC device usually requires a fixed pixel rate for the display device, and a fixed pixel depth for the pixel data stored in the frame buffer.
A computer graphics system may employ a memory display interface coupled to a digital to analog converter, rather than a RAMDAC device, to improve pixel processing flexibility. A memory display interface processes pixel data at programmable pixel rates and pixel depths, and implements special pixel functions. Pixel processing at programmable pixel rates enables support of display devices having differing resolutions, and support of VRAM frame buffers having differing access speeds. Processing of pixels having programmable pixel depths within the VRAM frame buffer increases software compatibility.
However, the synchronization of pixel data processing within the memory display interface is complicated by the variable pixel rates and pixel depths. Clock signals for synchronizing pixel data flow through the memory display interface must be generated for a wide range of frequencies. Moreover, the clock signals must have a known relationship to the video clock that synchronizes the video signals. Fixed delay circuits used in the past to meet set up and hold requirements of the various circuit elements may work at one frequency, but not at other frequencies. The problem is made worse by the fact that the speed of circuit elements varies with temperature, voltage, and process of manufacturer.
As will be described, the present invention is a method and apparatus for synchronizing pixel data flow within a memory display interface supporting programmable pixel depths, and supporting display devices requiring differing pixel rates.